Field Effect Transistor (FET): Synthesis Paper

I will be sharing with you all what I learned from Field Effect Transistor (FET) by watching a playlist on YouTube.

We have just finished learning what Bipolar Junction Transistor is all about. Now that we have incorporated all of what we have learned on BJT this is the time where we learn something new, something that is somewhat a continuation on the BJT which is the FET. The field effect transistor, FET is a key electronic component using within many areas of the electronics industry. The FET used in many circuits constructed from discrete electronic components in areas from RF technology to power control and electronic switching to general amplification. Since we have already talked about the BJT, we will then compare the difference between the two. Let’s remember that a BJT  is a one type of transistor that uses both majority and minority charge carriers. These semiconductor devices are available in two types such as PNP and NPN. BJT is a bipolar transistor meanwhile the FET is a uni polar transistor. It is also stated in the video that  Bipolar junction transistors are current controlled while Field effect transistors are voltage controlled. Well that is some of their differences that is easy to remember. Field effect transistors are classified into two types such as JFET and MOSFET. Just like the BJT which have three terminals namely: emitter, base and collector the FET also have three terminals which is the source, drain and gate. FETs are widely used as input amplifiers in oscilloscopes, electronic voltmeters and other measuring and testing equipment because of their high input impedance. As what the video also talked about whenever the ‘G’ terminal of the FET transistor has been charged, no more current is required to keep the transistor ON. The input impedance of field effect transistors has high compared with bipolar junction transistors. FET has a +Ve temperature coefficient for stopping over heating. FETS are applicable for low voltage applications. FETs have low to medium gain. As what I’ve said,  field effect transistors are classified into two types such as JFET and MOSFET. We will talk about the JFET first. JFET has a n-channel which is  JFET whose channel is composed of primarily electrons as the charge carrier. This means that when the transistor is turned on, it is primarily the movement of electrons which constitutes the current flow. An n-type channel is formed between two p-type layers which are connected to the gate. Majority carrier electrons flow from the source and exit the drain, forming the drain current.. A N-Channel JFET is composed of a gate, a source and a drain terminal. Now, let’s talk about the depletion layer. the depletion will be wider at the drain because it is connected to the positive of the battery whereas the source is at a voltage closer to that on the gate. As the gate gets more negative the depletion region will grow and eventually the device will be deemed to be "cut-off" and exhibit only low leakage currents from drain to source. The video also mentioned something about a water tap analogy where we Think about water coming out of a faucet. It is perfectly safe for normal use but contains minor impurities. You need to filter out those impurities if you desire entirely pure water.
Electricity works in the same manner. Even though Center Point Energy is dedicated to providing reliable and high quality electric service, there are occasional interruptions or fluctuations of power supply. There are also a lot of parts where we encountered solving all throughout  the video or the playlist that tackled the Field Effect Transistor and one of its types which is the JFET.

Pinch-off condition and pinch-off voltage are both mentioned in the video, so what are they all about? Pinch-off is not locked. During pinch-off operation, the discharge current does not drop to zero. Instead, the Id current becomes constant, remaining relatively independent of the Vds voltage. The pinch-off mode in FET transistors is similar to the linear operating region of the BJT transistors. While Pinch off voltage is the drain to source voltage after which the drain to source current becomes almost constant and JFET enters into saturation region and is defined only when gate to source voltage is zero. With the common-source common-source hook of a JFET to N channel, since gate voltage Vgs becomes more and more negative, the channel becomes narrower as the Mobile Depletion Zones invade the channel from the side.

And then, these Depletion Areas meet but the channel does not close! Instead, the channel becomes a long passage of constant width. Within this channel, avalanche breakdowns occur while small portions of the channel try to close. But every time this happens, a larger voltage appears through the closed portion, which brings the DZ back and opens the channel again.During pinch-off the channel behaves very strangely: it is no longer a resistance. Instead, when the drain-source Vds voltage increases, the conductive channel grows physically for longer! It is a magic resistor, a resistor that tries to maintain a constant current even against the variable voltages that lie on it. When you connect the gate to the source of a JFET (junction field-effect transistor), it becomes a two-terminal current source. The current that will flow is called IDSS (current, drain-to-source, saturated). One problem you might face is that the IDSS of FETs is quite variable for different parts of the same number. The size of the JFET will determine the rough range of the current, but it does change over temperature. JFETs are depletion-mode devices that conduct until you apply a negative voltage to the gate relative to the source. We will now tackle about the output characteristics or drain characteristics of the n-channel JFET. When in the absence of the external bias there is no voltage between gate and source terminal, thus, the drain current will flow from drain terminal to source terminal. We have already discussed in the working of JFET that majority charge carriers flow from source to drain and as a consequence of which the current flows from drain to source.Now, what does this means? It clearly implies that the channel width is more as the width of depletion layer will not vary initially because there is no external reverse biasing. This allows a large magnitude of current to flow through the channel. When the external bias is applied to the gate-source terminal, the gate-source terminal becomes reversed bias externally. Obviously, if we are supplying an external voltage, then we can achieve the pinch-off point quite early as compared to the circuit which is not biasedIt is clearly evident from the characteristics curve of external bias. The different values of voltage give different values of current. It is to be remembered here that when we are observing the drain characteristics with respect to the variation in drain-source voltage, then the value of gate-source voltage should be kept constant. In a p-channel JFET the source is positive with respect to the drain.The Ohmic Region is the only region on a FET Characteristics curve where there is a linear response in current from changes in the voltage. It is called the ohmic region, or linear region, because the JFET behaves like a voltage-controlled resistor. The region between the pinch-off voltage and avalanche breakdown is called the active region, amplifier operating region, saturation region, or pinch-off region. The ohmic region (before pinch-off) is usually called the triode region, but it is sometimes called the voltage-controlled region. The JFET is operated in the ohmic region both when a variable resistor is desired and in switching applications.The cutoff voltage (VGS,off), to turn a transistor off, is applied to the gate-source region of the FET transistor. It is the particular gate-source voltage where the JFET acts like an open circuit. And lastly, the Breakdown Region of a FET transistor is the region where the drain of the transistor receives too much voltage which causes the drain-source channel to breakdown and the drain current, ID drastically increases. Next, we will talk about JFET as a voltage controlled resistor. For a junction field-effect transistor (JFET) under certain operating conditions, the resistance of the drain-source channel is a function of the gate-source voltage alone and the JFET will behave as an almost pure ohmic resistor. Maximum drain-source current, IDSS, and minimum resistance rDS(on), will exist when the gate-source voltage is equal to zero volts (VGS = 0). If the gate voltage is increased (negatively for n-channel JFETs and positively for p-channel), the resistance will also increase. When the drain current is reduced to a point where the FET is no longer conductive, the maximum resistance is reached. The voltage at this point is referred to as the pinchoff or cutoff voltage and is symbolized by VGS = VGS(off). Thus the device functions as a voltage- controlled resistor. At the last video about JFET it tackled what is its transfer characteristics, The transfer characteristics can be determined by observing different values of drain current with variation in gate-source voltage provided that the drain-source voltage should be constant. The transfer characteristics are just opposite to drain characteristics. One just needs to remember the concept that in drain characteristics we are keeping the gate-source voltage constant and determining the values of drain current at different values of drain-source voltage while in transfer characteristics we are keeping the value of drain-source voltage constant. Overall, learning Field Effect Transistor online and not in school where there is an instructor guiding us is quite hard. I admit that most of the topics covered here are complicated and is hazy to me. It is challenging to learn all of them in a short span of time. But, I appreciated the videos that I have seen though but frankly speaking I don’t think that all of the informations above will retain to my mind. Although, I have learned things while watching the video it is still different when we have an Instructor teaching us. At least that’s what I prefer.

So here we are, the last topic for this synthesis paper. We’ve come a long way to be here. For a change, I decided to finish all the videos before making a synthesis paper about MOSFET. Unlike the first two topics which is the BJT and FET/JFET where I made the synthesis paper while watching the videos at the same time. So while watching the playlist I decided to write all of the the things that I’ve learned and it actually took me 2 days to finish all of them. So expect that it is a whole lot shorter than two previous topics.

So in contrast to the Junction Field Effect Transistor (JFET), the Insulated Gate Field Effect Transistor (IGFET) has its Gate input electrically insulated from the main current carrying channel. The most common type of insulated gate FET which is used in many different types of electronic circuits is called the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon dioxide, commonly known as glass. This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The isolation of the controlling Gate makes the input resistance of the MOSFET extremely high way up in the Mega-ohms (MΩ) region thereby making it almost infinite. As the Gate terminal is isolated from the main current carrying channel “NO current flows into the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the current flowing through the main channel between the Drain and Source is proportional to the input voltage. Also like the JFET, the MOSFETs very high input resistance can easily accumulate large amounts of static charge resulting in the MOSFET becoming easily damaged unless carefully handled or protected. Like the previous JFET tutorial, MOSFETs are three terminal devices with a Gate, Drain and  Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The main difference this time is that MOSFETs are available in two basic forms: Depletion Type – the transistor requires the GateSource voltage, (VGS) to switch the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch. Enhancement Type – the transistor requires a GateSource voltage, (VGS) to switch the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch.

The Depletion-mode MOSFET, which is less common than the enhancement mode types is normally switched “ON” (conducting) without the application of a gate bias voltage. That is the channel conducts when VGS = 0 making it a “normallyclosed” device. The circuit symbol shown above for a depletion MOS transistor uses a solid channel line to signify a normally closed conductive channel. For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete (hence its name) the conductive channel of its free electrons switching the transistor “OFF”. Likewise for a p-channel depletion MOS transistor a positive gate-source voltage, +VGS will deplete the channel of its free holes turning it “OFF”. In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and more current. While a -VGS means less electrons and less current. The opposite is also true for the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed” switch. The depletion-mode MOSFET is constructed in a similar way to their JFET transistor counterparts were the drain-source channel is inherently conductive with the electrons and holes already present within the n-type or p-type channel. This doping of the channel produces a conducting path of low resistance between the Drain and Source with zero Gate bias.

The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the depletion-mode type. Here the conducting channel is lightly doped or even undoped making it non-conductive. This results in the device being normally “OFF” (non-conducting) when the gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an enhancement MOS transistor uses a broken channel line to signify a normally open non-conducting channel. 2 For the n-channel enhancement MOS transistor a drain current will only flow when a gate voltage (VGS) is applied to the gate terminal greater than the threshold voltage (VTH) level in which conductance takes place making it a transconductance device. The application of a positive (+ve) gate voltage to a n-type MOSFET attracts more electrons towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the thickness of the channel allowing more current to flow. This is why this kind of transistor is called an enhancement mode device as the application of a gate voltage enhances the channel. Increasing this positive gate voltage will cause the channel resistance to decrease further causing an increase in the drain current, ID through the channel. In other words, for an n-channel enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a “normally-open” switch. The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is “OFF” and the channel is open. The application of a negative (-ve) gate voltage to the p-type eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor “ON”. Enhancement-mode MOSFETs make excellent electronics switches due to their low “ON” resistance and extremely high “OFF” resistance as well as their infinitely high input resistance due to their isolated gate. Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and power switching circuits in the form of as PMOS (P-channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary MOS meaning that the logic device has both PMOS and NMOS within its design.

Overall, BJT and FET are both interesting topics, how I wish I could learn it more properly than just watching a playlist. Online classes for me is not that effective compare to the face to face learning. Though, I appreciate the efforts of our instructor to give us the topics to learn and the most accessible and easiest way to compensate for this.